1. Field of the Invention
The present invention generally relates to the formation of integrated circuits, and, more particularly, to the formation of polysilicon lines, such as gate electrodes, requiring the exposure of upper sidewall portions thereof so as to provide an increased surface area for the formation of a metal silicide.
2. Description of the Related Art
Presently, the vast majority of integrated circuits is manufactured on the basis of silicon with critical feature sizes on the order of 0.1 μm and even less. The fabrication of transistor elements representing the dominant components of active circuits typically requires, among others, a controlled introduction of dopants into precisely defined silicon regions. One circuit architecture, which is currently the preferred technology owing to the superior performance with respect to power consumption, requires the formation of highly doped silicon regions with an inversely doped channel region disposed therebetween, wherein the conductivity of the channel region is controlled by an electric field generated by applying a control voltage to a gate electrode located in the vicinity of the channel region and separated therefrom by a gate insulation layer. Hence, a reduction in size of the transistor element necessitates the reduction of the distance between the highly doped silicon regions. This distance represents an important design criterion and is also referred to as the “channel length.” In currently favored CMOS technologies, the gate electrode is patterned prior to the formation of the highly doped silicon regions, also referred to as “drain region and source region,” so as to obtain the transistor geometry, i.e., the spatial relationship between the gate electrode, the drain region and the source region, in a self-aligned manner. Reducing the channel length, therefore, also requires a corresponding reduction of the size of the gate electrode. Generally, the gate electrode may be considered as a line-like circuit feature, the width of which is related to the corresponding channel length and is thus also referred to as the “gate length.”
Since the formation of the transistor elements, especially the creation of an appropriately-shaped dopant profile in the drain and source regions, requires a plurality of high temperature processes, polysilicon is the preferred material for the gate electrode due to the superior and well understood characteristics of the silicon/silicon dioxide interface as silicon dioxide is frequently used as the gate insulation layer separating the channel region from the gate electrode. Although the provision of the polysilicon gate electrode prior to the formation of the drain and source regions assures a self-aligned transistor geometry, it turns out that complex, precisely-defined dopant profiles in the lateral direction are necessary to provide the required transistor performance of extremely scaled transistor devices. For this reason, so-called “sidewall spacers” are formed on sidewalls of the gate electrode, which may be considered as dielectric extensions of the gate electrode so as to correspondingly design the lateral dimensions of the gate electrode, which acts as an implantation mask during a plurality of implantation sequences for creating the required dopant profile. Since the dimensions of the sidewall spacers substantially determine the finally obtained dopant profile, the formation of the sidewall spacers may be carried out in two steps so as to provide superior process control during the formation of a first sidewall spacer and a subsequent formation of a second sidewall spacer, wherein, depending on process requirements, corresponding implantation cycles may be performed during the various stages of the spacer fabrication process.
With reference to FIGS. 1a–1d, a typical conventional process flow for forming a gate electrode is described, including first and second sidewall spacers so as to provide a lateral dopant profile required for extremely scaled transistor devices.
In FIG. 1a, a transistor element 100 comprises a substrate 101, for instance a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, including a crystalline silicon region 103, which also may be referred to as an “active region,” that is enclosed by an isolation structure 102 that is usually provided in the form of a trench isolation structure in sophisticated devices. A polysilicon gate electrode 104 is formed on a gate insulation layer 105, for instance, provided in the form of a silicon dioxide layer, which separates the gate electrode 104 from a channel region 106. The horizontal extension of the gate electrode 104 in FIG. 1a is referred to as the “gate length.” A dielectric liner 107 comprised of silicon dioxide is formed on the sidewalls 109 of the gate electrode 104 as well as on the top surface thereof and on other surface portions of the transistor 100. Furthermore, recessed sidewall spacers 108 are formed on the liner 107 so as to not cover an upper portion 110 of the gate electrode 104.
A typical process flow for forming the transistor 100 as shown in FIG. 1a may include the following processes. After formation of the trench isolation structure 102 by means of sophisticated photolithography, etch and deposition techniques, implantation cycles may be performed so as to provide a required vertical dopant profile (not shown) in the active region 103. Thereafter, an insulating layer having a required thickness and composition suitable for the gate insulation layer 105 may be formed, for instance by well-established oxidation and/or deposition techniques. Next, a polysilicon layer of a specified thickness may be deposited and patterned in combination with the insulating layer by highly advanced photolithography and etch techniques so as to form the gate electrode 104 and gate insulation layer 105. Then, an ion implantation process may be performed to form doped extension regions 111, wherein the gate electrode 104 is used as an implantation mask. Thereafter, the liner 107 may be formed, for instance by the deposition of silicon dioxide, or by an oxidation process. Subsequently, a silicon nitride layer is conformally deposited with a predefined thickness that substantially determines a finally obtained width of the sidewall spacer 108. Thereafter, the silicon nitride layer is anisotropically etched with an etch chemistry that exhibits a high selectivity with respect to silicon dioxide. During the anisotropic etch process, the etch time may be controlled so as to adjust a degree of recessing the sidewall spacer 108, thereby determining the size of the exposed upper sidewall portion 110. Due to the high etch selectivity provided by the etch chemistry, the etch process is reliably stopped on exposed portions of the silicon dioxide liner 107. After recessing the sidewall spacer 108, the transistor 100 is exposed to a further anisotropic etch atmosphere comprised of an etch chemistry that removes silicon dioxide selectively to silicon.
FIG. 1b schematically shows the transistor device 100 after completion of the anisotropic silicon dioxide etch process. Due to the anisotropic nature of the silicon dioxide etch, the upper sidewall portion 110 is not completely exposed, resulting in silicon dioxide residues 112. After the formation of the sidewall spacers 108, a further ion implantation cycle may be performed so as to correspondingly modify the lateral dopant profile in the regions 111 or, depending upon the process technology used, a second sidewall spacer may be formed prior to carrying out the respective implantation cycles so as to obtain the desired lateral dopant profile. Providing a first sidewall spacer, i.e., the sidewall spacer 108, prior or between sophisticated implantation cycles may significantly improve the overall transistor characteristics in that the spacer width may be controlled more precisely and/or the dopant profile may be modified with a finer lateral “resolution.”
FIG. 1c schematically shows the transistor device 100 in an advanced manufacturing stage, wherein second sidewall spacers 115 comprised of silicon nitride are formed at the first sidewall spacers 108, wherein a further liner oxide 114 separates the spacers 108 and 115. As previously explained, by means of the first and second sidewall spacers 108 and 115, the lateral dopant profile in the active region 103 may be appropriately shaped so as to form the extension 111 and corresponding drain and source regions 113. Moreover, the sidewall spacers enable the formation of highly conductive metal silicide on the drain and source regions 113 and on the gate electrode 104 in a self-aligned manner. Although the gate electrode 104 has received a dopant dose corresponding to the dose used to form the drain and source regions 113 and the extension 111, the resistance of polysilicon is still significantly higher than a metal, such as aluminum, and may lead to an intolerable signal propagation delay during operation of the device 100. Especially, as the gate length is reduced, the reduced cross-sectional area, in combination with an insufficient doping concentration in the vicinity of the gate insulation layer 105, may therefore lead to an increased gate line resistance.
In an attempt to reduce the resistivity of doped silicon regions, it has become standard practice to form a metal silicide on the drain and source regions 113 and the gate electrode 104. Since these metal silicide regions are formed in a common process sequence, the depth of the metal silicide formed on the gate electrode 104 is restricted by the depth of the drain and source regions 113 as the metal silicide may not extend into the inversely doped active region 103. As a matter of fact, a reduced gate length, and thus a reduced transistor dimension, however, requires the provision of extremely shallow source and drain regions 113 in combination with an extremely thin gate insulation layer so as to assure the desired controllability of the transistor 100. Consequently, the corresponding thickness of a metal silicide region on top of the gate electrode 104 is restricted by the requirements of shallow drain and source regions and thus the increase in resistivity of a dimensionally scaled gate electrode may not be compensated for as efficiently as is required. Therefore, the upper portion 110 of the sidewall 109 is exposed so as to provide an increased diffusion path during the chemical reaction between the metal and silicon in the gate electrode 104, thereby providing an increased metal silicide region therein. For this reason, the first and second spacers 108 and 115 are recessed to allow the exposure of an increased surface portion of the gate electrode 104 while providing the required lateral shaping of the dopant profile.
Thus, after removing the exposed portions of the silicon dioxide liner 114 by a selective anisotropic etch process and a subsequent cleaning process for removing oxide residues, a refractory metal, such as cobalt, is deposited over the transistor 100 and a heat treatment is performed to initiate a chemical reaction between the refractory metal and the silicon.
FIG. 1d schematically shows the transistor 100 with a cobalt layer 116 formed thereon. Even though a clean process is performed, the residues 112, 117 of the liner oxides 107 and 114 may still be present, resulting from the preceding anisotropic selective etch process. Hence, the upper sidewall portion 110 is not completely exposed and thus the cobalt diffusion is significantly hindered, resulting in a reduced cobalt silicide formation. Since the height of the first and the second spacers 108 and 115 may not be reduced arbitrarily so as to not unduly compromise the blocking effect during the implantation cycles, the silicon dioxide residues 112, 117 remarkably compromise the effective increase of conductivity.
Therefore, a need exists for an improved technique that enables the formation of recessed sidewall spacers, wherein at least some of the problems identified above may be eliminated or at least significantly reduced.